HDI · Via Structures · Special Processes
PCB Capability Limits Explained
Capability is not a yes-or-no question — it is a boundary where the standard process ends and an advanced tier begins. This guide maps those boundaries: microvias and HDI stack-ups, blind and buried vias, via-in-pad, gold fingers, castellated holes and controlled impedance — what each one costs in process terms, and how to confirm your design sits inside the line before you lock the layout.
- HDI In-House Laser-drilled microvias and sequential lamination on our own lines
- Impedance Verified Stack-up modeling at quote stage, TDR coupons on the panel
- Free Capability Review Every advanced-process inquiry gets an engineer's feasibility answer
Quick Answer · Scope · Boundary Reference
Every Limit Is a Process Boundary
This guide covers bare board fabrication limits — the features that decide which process tier your job runs on. Assembly-side constraints (component pitch, package types) are a separate scope.
A fabricator's capability sheet is not a list of yes/no answers. Inside the standard tier, features cost nothing extra because the default process already produces them. Each boundary you cross — a smaller hole, a laser-drilled microvia, a filled via-in-pad, hard gold on an edge connector — moves the job to a more specialized tier with different equipment, extra steps and a different yield profile. Knowing where the boundaries sit lets you spend advanced-process budget only where the circuit genuinely needs it.
What This Guide Covers
- Through-hole limits: minimum drill size and aspect ratio
- HDI structures: microvias, stacked vs staggered, 1+n+1 and beyond
- Blind and buried vias and sequential lamination
- Via-in-pad: when it is needed and what filling adds
- Edge features: gold fingers, beveling, castellated holes, edge plating
- Controlled impedance tiers and how they are verified
What This Guide Is Not
- A capability certificate — the current sheet is on the capabilities page
- Assembly-side limits (component pitch, packages, test access)
- A design-rule tutorial — the DFM guide covers standard rules
- A material selection guide — the materials guide covers laminates
- A guarantee that a feature at the limit ships at standard price
For standard design rules, see the PCB DFM Guide; for laminate selection behind impedance and HDI builds, see the Materials & Stackup Guide. Assembly-side capability belongs to our partner JHYPCB.
Process Boundary Quick Reference
| Feature | Standard Tier | Advanced Tier Boundary |
|---|---|---|
| Mechanical drill | ≥ 0.20 mm finished hole | Below ~0.15 mm or aspect ratio beyond 8:1 → laser or special drilling |
| Microvia (laser) | Not in standard tier | ~0.10 mm laser via, staggered preferred; stacked adds process risk |
| Blind / buried via | Not in standard tier | Each buried span adds a lamination cycle — cost scales with cycles |
| Via-in-pad | Standard pads only | Fine-pitch BGA fan-out → conductive fill + planarization required |
| Trace / space (HDI) | ≥ 3/3 mil standard tier | Below 3/3 mil moves to fine-line imaging tier |
| Gold fingers | ENIG pads standard | Insertion cycles → hard gold 3–30 µin + bevel, called out on drawing |
| Castellated holes | Not in standard tier | ≥ 0.60 mm half-hole diameter for reliable plating and routing |
| Controlled impedance | ±10% typical tier | ±5% tight tier — narrower process window, TDR verification required |
Boundary values are orientation from common industry tiers, not our certified limits. The quotation confirms the tier your files actually fall into.
Inside the Boundaries · Six Process Areas
The Six Boundaries That Define the Tier
Most "can you make this?" questions land on one of these six areas. Each card explains what crossing the boundary involves in process terms, and links to a detailed article from our engineering blog.
Boundary 01 · HDI
Microvias Change the Whole Build
Laser-drilled microvias are not just smaller holes — they change the stack-up, the plating chemistry and the lamination sequence. Staggered microvias are the safer tier; stacked vias demand tighter process control and cost accordingly.
Microvias Explained: Types & Design RulesBoundary 02 · Via Spans
Blind & Buried Vias Add Lamination Cycles
A through-hole is drilled once after final lamination. Every blind or buried span must be drilled and plated before the layers around it are laminated — each additional span is another cycle of drilling, plating and pressing.
PTH, Blind & Buried Vias ComparedBoundary 03 · Fan-Out
Via-in-Pad Needs Filling to Be Reliable
Routing a via directly in a BGA pad saves space but traps solder — the joint wicks down the barrel. The reliable tier is conductive or resin fill with planarization and a plated-over cap, which is a separate process step.
Via-in-Pad: Identification & ProcessingBoundary 04 · Edge Connectors
Gold Fingers Are a Mechanical System
Insertion-cycle rating decides hard gold thickness; the bevel angle decides how the connector seats; the panelization decides whether the fingers survive depaneling undamaged. All three are specified together or not at all.
Gold Finger Design & Manufacturing GuideBoundary 05 · Module Edges
Castellated Holes Have a Minimum Size
Half-holes on the board edge let a module solder down like a component — but below a minimum diameter the plated barrel cannot survive routing intact. Diameter, pad ring and edge spacing are the three numbers to confirm.
Castellated Holes in PCB DesignBoundary 06 · Signals
Impedance Is a Tolerance Game
Controlled impedance is not a material property — it is geometry plus laminate plus process control, held within a stated tolerance. The ±5% tier narrows every window: dielectric thickness, trace width etch compensation and TDR verification.
High-Frequency Design & Impedance ControlMultilayer builds multiply the boundaries
Every advanced feature interacts with the lamination sequence — see how a multilayer board is actually built: How to Build a Multilayer PCB.
Before You Specify · Capability Checklist
Eight Checks Before You Lock an Advanced Process
Advanced processes fail at the specification stage, not on the production line. These eight checks catch the mismatches — between what the layout assumes and what the process can hold — while changes are still cheap.
| Check | Why It Matters | What to Do |
|---|---|---|
| Justify the microvia structure | Stacked microvias cost and risk more than staggered; 2+n+2 costs more than 1+n+1. | Start from the fan-out requirement, not from the most impressive stack-up |
| Check hole size against aspect ratio | A small hole in a thick board exceeds the plating aspect ratio long before it exceeds the drill limit. | Divide board thickness by finished hole diameter — stay inside the tier |
| Count the lamination cycles | Every blind/buried span adds a drill-plate-press cycle; cycles drive both cost and lead time. | Ask which spans need separate cycles before finalizing the stack-up |
| Specify via-in-pad fill explicitly | An unfilled via-in-pad wicks solder and fails at assembly — but fill is not the default. | State "conductive fill, planarized, capped" in the fab notes where required |
| Call out gold finger parameters | Hard gold thickness, bevel angle and chamfer length are not inferred from the Gerber. | Put insertion cycles, gold thickness and bevel on the fabrication drawing |
| Respect castellated minimums | Half-holes below the minimum diameter lose their barrel during routing. | Confirm diameter and pad ring against the routing process |
| State the impedance tolerance | "Controlled impedance" without a tolerance defaults to the wider tier — or triggers a question. | Name target ohms, tolerance and reference layers; request TDR coupons |
| Ask before designing at the limit | A feature at the absolute limit everywhere on the panel compounds yield loss. | Send the stack-up and key features for a free capability review first |
Every advanced-process RFQ to PCBELEC gets a feasibility answer from an engineer — if a feature needs a different tier or a small relaxation to be manufacturable, you hear it before the layout is final.
Not sure which tier your design falls into? Send the stack-up and the critical features — the capability review tells you exactly where the boundaries are for your board.
Request a Capability CheckCapability Library · From Our Engineering Blog
Go Deeper on Vias, Edge Features & Advanced Builds
These articles expand each boundary above — via structures and HDI, gold fingers and edge features, and the impedance, flex and rigid-flex constructions where limits interact. Part of the PCBELEC fabrication knowledge base.
Avoid These · Three Common Mistakes
Where Advanced Specifications Usually Go Wrong
Most advanced-process failures are specified into the design weeks before fabrication starts. These three patterns cause the respins we see most often.
Mistake 01
Designing at the Limit Everywhere
Minimum hole, minimum trace, tightest tolerance — applied across the whole board "to be safe". Each limit feature individually passes review; together they compound yield loss across the panel, and the price quietly moves to the next tier for no functional gain.
Instead: use limit features only where the circuit forces them. The rest of the board belongs in the standard tier — that is where yield and price are best.
Mistake 02
Assuming Via-in-Pad Is Standard
The Gerber shows a via inside a pad and the fabricator builds exactly that — an open barrel that wicks solder at assembly. Filling, planarizing and capping are separate process steps that are never inferred; they must be specified, and they change both cost and lead time.
Instead: state the fill requirement in the fabrication notes for every via-in-pad, and confirm the fill type with the fabricator before ordering.
Mistake 03
Leaving Special Features Out of the Fab Notes
Gold finger bevel angles, castellated hole intent, impedance targets, controlled-depth drills — none of these are reliably readable from Gerber data alone. Features that exist only in the designer's head get built to default assumptions, and default assumptions build scrap.
Instead: every non-standard feature goes on the fabrication drawing with its parameters. The checklist above lists what each feature needs.
FAQ · Capability & Limits Questions
Frequently Asked Questions About PCB Capability Limits
Short answers to the questions engineers ask before specifying an advanced process. For a definite answer on your specific construction, send the stack-up below.
What is the difference between HDI and a standard multilayer board?
A standard multilayer board uses mechanically drilled through-holes and conventional lamination. HDI adds laser-drilled microvias, finer lines and spaces, and often blind or buried via structures with sequential lamination. The practical trigger is fan-out density: when a fine-pitch component cannot be routed with through-holes, the design has already chosen HDI — the question is only which tier (1+n+1, 2+n+2) is sufficient.
When do I actually need blind or buried vias?
When routing density demands them — typically when a through-via would block a routing channel on a layer it does not connect to, or when a high-layer-count board cannot escape its BGA fan-out any other way. Each buried span adds a lamination cycle, so the cost case has to come from routing necessity. If a through-via with a smaller pad works, it is almost always the cheaper answer.
Is via-in-pad always required for fine-pitch BGA?
No — it depends on pitch. Coarser BGA pitches can often fan out with dog-bone traces to a via beside the pad, which stays in the standard tier. Below roughly 0.5 mm pitch, via-in-pad usually becomes unavoidable, and then the fill specification becomes critical: conductive fill, planarized and capped, stated explicitly in the fabrication notes. The layout decision and the process specification have to be made together.
Hard gold or ENIG for gold fingers?
Insertion cycles decide. ENIG gold is thin and wears through after a small number of insertions — fine for a board plugged once at assembly. Edge connectors that mate repeatedly need electrolytic hard gold, with the thickness matched to the cycle rating and a bevel to protect the connector and the plating. State the expected insertion cycles on the drawing and the thickness follows from that.
What tolerance can controlled impedance hold?
±10% is the widely available tier for typical constructions; ±5% is achievable but narrows every process window — dielectric thickness, etch compensation, laminate batch — and requires TDR coupon verification on the panel. Specify the tightest tolerance your signals actually need, not tighter: over-specifying impedance tolerance buys cost and yield risk with no signal-integrity benefit.
How do I confirm my design is within capability before ordering?
Send the stack-up drawing and the critical features — minimum hole, trace/space, via structures, edge features, impedance targets — with your RFQ. Our engineers review every advanced-process inquiry for feasibility and come back with the tier your design falls into, any feature that needs relaxation, and the cost impact. That review is free and happens before you commit to the layout.
Feasibility First · Capability Check
Get a Capability Check With Your Quote
Send the stack-up and the critical features. An engineer confirms which tier your design falls into, flags anything that needs relaxation before it becomes a yield problem, and quotes the construction that actually matches your requirements.
What to Include in Your RFQ
- Gerber/ODB++ and drill files, plus the stack-up drawing
- Minimum hole size, trace/space and board thickness
- Via structures: blind/buried spans, microvia tiers, via-in-pad locations
- Edge features: gold finger cycles and bevel, castellated hole size
- Impedance targets with tolerances and reference layers
- Quantity and target delivery date
Not sure the package is complete? Check the manufacturing file requirements first, or review the current technical capabilities sheet.
Need Assembly for Advanced Builds?
PCBELEC fabricates the bare boards — including HDI and rigid-flex. Turnkey assembly of fine-pitch and BGA designs is handled by our partner JHYPCB. Mention it in your inquiry and we will coordinate both sides.
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